The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Jun. 03, 2016
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Da-Wei Lai, Nijmegen, NL;

Guido Wouter Willem Quax, Utrecht, NL;

Gijs Jan De Raad, Nijmegen, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 3/22 (2006.01); H02H 9/04 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01); H01L 27/0255 (2013.01); H01L 27/0262 (2013.01); H01L 27/0266 (2013.01); H01L 27/0285 (2013.01);
Abstract

An electrostatic discharge power rail clamp circuit and an integrated circuit including the same. The power rail clamp circuit includes a first power rail, a second power rail and a first node. The circuit further includes an n-channel field effect transistor having a source and drain located in an isolated p-well in a semiconductor substrate. The drain is connected to the first power rail. The source and isolated p-well are connected to the first node. The circuit also includes a capacitor connected between the first node and the second power rail. The circuit further includes a resistor connected between the first power rail and the first node. The circuit also includes an inverter for controlling the gate of the field effect transistor, wherein the inverter has an input connected to the first node. The circuit further a silicon controlled rectifier connected between the first node and the second power rail.


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