The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2018
Filed:
Aug. 23, 2013
Qualcomm Incorporated, San Diego, CA (US);
Seid Hadi Rasouli, San Diego, CA (US);
Michael Joseph Brunolli, Escondido, CA (US);
Christine Sung-An Hau-Riege, Fremont, CA (US);
Mickael Malabry, San Diego, CA (US);
Sucheta Kumar Harish, San Diego, CA (US);
Prathiba Balasubramanian, Bangalore, IN;
Kamesh Medisetti, Bangalore, IN;
Nikolay Bomshtein, San Diego, CA (US);
Animesh Datta, San Diego, CA (US);
Ohsang Kwon, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.