The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Oct. 06, 2015
Applicant:

Taiyo Yuden Co., Ltd., Tokyo, JP;

Inventors:

Hideaki Yoshida, Tokyo, JP;

Mitsunori Katsu, Tokyo, JP;

Hiroyuki Kozutsumi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); H01L 21/82 (2006.01); G01R 31/28 (2006.01); G06F 17/50 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82 (2013.01); G01R 31/2884 (2013.01); G01R 31/318516 (2013.01); G06F 17/5027 (2013.01); G11C 11/4076 (2013.01); G11C 11/4082 (2013.01); H03K 19/177 (2013.01);
Abstract

A reconfigurable device and an analog circuit are formed on a single chip so that the analog circuit can be controlled by the reconfigurable device. A reconfigurable semiconductor device () includes a plurality of logic sections () and an analog section (). The plurality of logic sections () are connected to each other by an address line or a data line. The analog section () includes a plurality of input/output sections and an output amplifier. Each of the logic sections () includes a plurality of address lines, a plurality of data lines, a memory cell unit, and an address decoder that decodes an address signal and that outputs a decoded signal to the memory cell unit. The plurality of logic sections () and the analog section () are mounted in the same chip package.


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