The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2018
Filed:
May. 26, 2017
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Assignee:
Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 29/12 (2006.01); G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 8/16 (2006.01); G11C 11/406 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 11/412 (2006.01); G11C 29/02 (2006.01); G11C 29/18 (2006.01);
U.S. Cl.
CPC ...
G11C 29/12 (2013.01); G11C 7/1075 (2013.01); G11C 8/10 (2013.01); G11C 8/16 (2013.01); G11C 11/406 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 29/025 (2013.01); G11C 29/12015 (2013.01); G11C 29/18 (2013.01); G11C 2029/1202 (2013.01);
Abstract
A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.