The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Jun. 29, 2017
Applicant:

Everspin Technologies, Inc., Chandler, AZ (US);

Inventors:

Thomas Andre, Austin, TX (US);

Syed M. Alam, Austin, TX (US);

Chitra Subramanian, Mahopac, NY (US);

Assignee:

EVERSPIN TECHNOLOGIES, INC., Chandler, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G11C 7/06 (2006.01); G11C 7/02 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1675 (2013.01); G11C 7/02 (2013.01); G11C 7/065 (2013.01); G11C 11/16 (2013.01); G11C 11/1655 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); G11C 11/1693 (2013.01); G11C 2013/0057 (2013.01); G11C 2207/002 (2013.01);
Abstract

An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.


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