The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2018
Filed:
Jul. 24, 2015
Ecole Polytechnique Federale DE Lausanne (Epfl), Lausanne, CH;
Xifan Tang, Lausanne, CH;
Pierre-Emmanuel Julien Marc Gaillardon, Renens, CH;
Giovanni De Micheli, Lausanne, CH;
Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, CH;
Abstract
A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 to k+1, and whereby (a) an output of a LUT, 1≤i≤k, connects to one of the inputs of routing multiplexers of LUT, i<j≤k+1, hence creating a fast interconnection between LUTs, each routing multiplexer of LUT, 2≤m≤k+1, has only one input that is connected to the output of an other LUT, the output of LUTbeing devoid of any connection to any one of the inputs of the routing multiplexers; (b) a subset of the inputs of LUTare connected to the outputs of other LUTs by means of fast interconnections, leaving the remaining inputs of LUTfree of any fast interconnection, whereby for LUT, 2≤p≤k+1, p−1 inputs of the LUTare connected to the outputs of LUT, 1≤q≤j, by means of fast interconnections; and (c) a cluster-based logic block contains at least one group of LUTs.