The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Feb. 22, 2013
Applicants:

Universite DE Bretagne Sud, Lorient, FR;

Centre National DE LA Recherche Scientifique—cnrs, Paris, FR;

Inventors:

Philippe Coussy, Ploemeur, FR;

Cyrille Chavet, Lorient, FR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/06 (2006.01); H03M 13/27 (2006.01); H03M 13/00 (2006.01); G06F 13/28 (2006.01); H03M 13/11 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0607 (2013.01); G06F 13/28 (2013.01); H03M 13/2764 (2013.01); H03M 13/2775 (2013.01); H03M 13/2789 (2013.01); H03M 13/6513 (2013.01); H03M 13/6519 (2013.01); H03M 13/6569 (2013.01); G06F 2212/251 (2013.01); H03M 13/1102 (2013.01);
Abstract

A device for interleaving/deinterleaving digital data delivered by processing elements (P0 . . . Pn-1) suitable for being used both with turbo-codes and with LDPC codes. The device includes memory banks (B0 . . . Bm-1) for storing data coming from or going to the processing elements, an interconnection network (INT) for directing the data between the processing elements and the memory banks, and a control unit (CTRL) for controlling the interconnection network and the memory banks. The control unit (CTRL) includes a calculation circuit (CAL) capable of the online generation of command words for the interconnection network and addressing and control sequences of the memory banks, ensuring conflict-free memory access on the basis of the interleaving rule to be applied, the size of the digital data frames, the number of processing units and memory banks, and the interconnection network.


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