The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2018
Filed:
Mar. 27, 2015
Qualcomm Incorporated, San Diego, CA (US);
Nishi Bhushan Singh, Bangalore, IN;
Anand Bhat, Bangalore, IN;
Ashutosh Anand, Bangalore, IN;
Rajesh Tiwari, Bangalore, IN;
Abhinav Kothiala, Bangalore, IN;
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A method and apparatus for reducing memory built-in self-test (MBIST) area by optimizing the number of interfaces required for testing a given set of memories is provided. The method begins when memories of a same configuration are grouped together. One memory is then selected from each of the groups. MBIST insertion is then performed for a selected group of memories, and the selected group of memories contains memories of different configurations. Control logic is used to select each group of memories separately. The memory group under test may also be selected using programmable user bits. An apparatus is also provided. The apparatus includes: a controller, at least one memory interface in communication with the controller, at least one control logic cloud in communication with the at least one memory interface; and at least one bit bus.