The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Mar. 09, 2017
Applicant:

Bell and Howell, Llc, Durham, NC (US);

Inventors:

Brian Bowers, Mundelein, IL (US);

Richard A. Yankloski, Webster, NY (US);

Assignee:

Fluence Automation LLC, Wheeling, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B41J 3/28 (2006.01); G06K 1/12 (2006.01); G06K 19/06 (2006.01); G07B 17/00 (2006.01);
U.S. Cl.
CPC ...
B41J 3/28 (2013.01); G06K 1/121 (2013.01); G06K 19/06037 (2013.01); G07B 17/0008 (2013.01); G07B 17/00467 (2013.01); G07B 17/00508 (2013.01); G06K 2019/06253 (2013.01); G07B 2017/0058 (2013.01); G07B 2017/00475 (2013.01); G07B 2017/00701 (2013.01);
Abstract

Assemblies, systems, and methods for applying postage indicia to one or more sequential mailpiece on a high speed mail sorter are disclosed. In some aspects, a system for franking one or more sequential mailpiece using a postal security device (PSD) hub assembly on a high speed mail sorter includes a plurality of PSDs configured to generate a coded digital signature for the one or more sequential mailpiece during a latency period, a plurality of photo sensors configured to define the latency period, a PSD host configured to receive the generated coded digital signature, wherein the generated coded digital signature is encoded in a data matrix, and an indicia printer configured to receive printer control data and to print the printer control data on the one or more sequential mailpiece in an order in which the plurality of PSDs are tasked during the latency period.


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