The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

Jun. 03, 2016
Applicants:

Ji-kyum Kim, Gyeonggi-do, KR;

Dae-seong Lee, Busan, KR;

Min-su Kim, Hwaseong-si, KR;

Inventors:

Ji-Kyum Kim, Gyeonggi-do, KR;

Dae-Seong Lee, Busan, KR;

Min-Su Kim, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/356 (2006.01); H03K 3/3562 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
H03K 3/35625 (2013.01); G01R 31/318541 (2013.01);
Abstract

A semiconductor integrated circuit includes a scan enable (SE) inverter and a clock (CK) inverter on a substrate, a first multiplex part, and a second multiplex part. The SE inverter and the CK inverter are aligned in a first direction. The first multiplex part includes a first wiring and a first transistor, the first wiring is connected to a power supply voltage part of the SE inverter, and the first wiring and the first transistor share a source region contacting the first wiring. The second multiplex part includes a second wiring and a second transistor, the second wiring is connected to a power supply voltage part of the CK inverter, and the second wiring and the second transistor share a source region contacting the second wiring. The SE inverter and the CK inverter are aligned in a first direction to each other.


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