The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

Apr. 17, 2017
Applicant:

Richtek Technology Corporation, Zhubei, HsinChu, TW;

Inventors:

Chien-Yang Chen, Taipei, TW;

Ta-Yung Yang, Taoyuan, TW;

Yu-Wen Chang, Nantou, TW;

Assignee:

RICHTEK TECHNOLOGY CORPORATION, Zhubei, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 1/15 (2006.01); H02M 7/06 (2006.01); H02M 1/32 (2007.01); H05B 33/08 (2006.01);
U.S. Cl.
CPC ...
H02M 1/15 (2013.01); H02M 1/32 (2013.01); H02M 7/06 (2013.01); H05B 33/0809 (2013.01); H05B 33/089 (2013.01); H05B 33/0815 (2013.01);
Abstract

The present invention discloses a switching regulator capable of reducing current ripple and a control circuit thereof. The switching regulator includes a buck power stage circuit and a control circuit. The control circuit includes an operation signal generation circuit and a current source circuit for reducing current ripple. The current source circuit is coupled to the operation signal generation circuit and the buck power stage circuit, for operating a ripple reduction switch therein according to an operation signal, to convert the output voltage to a load voltage between a load node and a reference node, and to reduce a current ripple of the output current, so as to generate a load current which is supplied to a load circuit, wherein the load circuit is coupled between the load node and the reference node, and the current source circuit is coupled between the output node and the load node.


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