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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9966455 B1

PDFFull Text
Date of Patent:
May. 08, 2018

Filed:

Jul. 24, 2017

Method for manufacturing a semiconductor device

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Seiji Muranaka, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

Mattingly & Malur, PC

Primary Examiner:

David S Blum

Int. Cl.
CPC ...
H01L 21/338 (2006.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 21/265 (2006.01); H01L 21/3105 (2006.01); H01L 21/3213 (2006.01); H01L 29/45 (2006.01); H01L 21/02 (2006.01); H01L 21/67 (2006.01); H01L 21/324 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/02068 (2013.01); H01L 21/26513 (2013.01); H01L 21/31053 (2013.01); H01L 21/32134 (2013.01); H01L 21/67057 (2013.01); H01L 21/67086 (2013.01); H01L 29/0847 (2013.01); H01L 29/45 (2013.01); H01L 21/0214 (2013.01); H01L 21/02164 (2013.01); H01L 21/324 (2013.01); H01L 29/0649 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01);
Abstract

The reliability of a semiconductor device is improved. A first gate electrode of a dummy gate electrode including silicon is formed over a semiconductor substrate. Then, by an ion implantation method, a semiconductor region for source or drain of MISFET is formed in the semiconductor substrate. Then, over the semiconductor substrate, an insulation film is formed in such a manner as to cover the first gate electrode. Then, the insulation film is polished to expose the first gate electrode. Then, the surface of the first gate electrode is wet etched by APM. then, the first gate electrode is removed by wet etching using aqueous ammonia. Thereafter, a gate electrode for MISFET is formed in a region from which the first gate electrode has been removed.

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