The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2018
Filed:
Mar. 31, 2016
Applicant:
Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, Guangdong, CN;
Inventor:
Shimin Ge, Guangdong, CN;
Assignee:
SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Shenzhen, Guangdong, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); G02F 1/1343 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4908 (2013.01); G02F 1/1343 (2013.01); H01L 29/0653 (2013.01); H01L 29/41733 (2013.01); H01L 29/66969 (2013.01); H01L 29/785 (2013.01); H01L 29/78618 (2013.01);
Abstract
A dual-gate TFT (thin film transistor) array substrate and a manufacturing method thereof are provided. A source electrode and a drain electrode are formed on a common electrode layer; and a common electrode of the common electrode layer, the source electrode and the drain electrode can simultaneously be formed by one mask during manufacturing. Therefore, the dual-gate TFT array substrate and the manufacturing method thereof have beneficial effects to reduce the number of masks, shorten the process, and improve the manufacturing efficiency.