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H01L 29/76 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 29/66 (2006.01);

U.S. Cl.

CPC ...

H01L 29/41791 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 29/41775 (2013.01); H01L 29/6653 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);

Abstract

There is provided a semiconductor device to enhance operating characteristics by reducing parasitic capacitance between a gate electrode and other nodes. The semiconductor device includes: a substrate including an active region, and a field region directly adjacent to the active region; a first fin-type pattern protruding from the substrate in the active region; a first gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a first portion and a second portion, the first portion intersecting with the first fin-type pattern; a second gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a third portion and a fourth portion, the fourth portion facing the second portion, and the third portion intersecting with the first fin-type pattern and facing the first portion; a first interlayer insulating structure disposed between the first portion and the third portion, being on the substrate, and having a first dielectric constant; and a second interlayer insulating structure disposed between the second portion and the fourth portion, being on the substrate, and having a second dielectric constant which is different from the first dielectric constant.

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