The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2018
Filed:
Feb. 22, 2016
Yong-joon Choi, Seoul, KR;
Tae-yong Kwon, Suwon-si, KR;
Mirco Cantoro, Suwon-si, KR;
Chang-jae Yang, Seoul, KR;
Dong-hoon Khang, Daegu, KR;
Woo-ram Kim, Seoul, KR;
Cheol Kim, Hwaseong-si, KR;
Seung-jin Mun, Suwon-si, KR;
Seung-mo Ha, Seoul, KR;
Do-hyoung Kim, Hwaseong-si, KR;
Seong-ju Kim, Suwon-si, KR;
So-ra You, Cheonan-si, KR;
Woong-ki Hong, Suwon-si, KR;
Yong-Joon Choi, Seoul, KR;
Tae-Yong Kwon, Suwon-si, KR;
Mirco Cantoro, Suwon-si, KR;
Chang-Jae Yang, Seoul, KR;
Dong-Hoon Khang, Daegu, KR;
Woo-Ram Kim, Seoul, KR;
Cheol Kim, Hwaseong-si, KR;
Seung-Jin Mun, Suwon-si, KR;
Seung-Mo Ha, Seoul, KR;
Do-Hyoung Kim, Hwaseong-si, KR;
Seong-Ju Kim, Suwon-si, KR;
So-Ra You, Cheonan-si, KR;
Woong-ki Hong, Suwon-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-Do, KR;
Abstract
A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.