The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

May. 25, 2017
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Salvatore Polizzi, Palermo, IT;

Giovanni Campardo, Bergamo, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); G11C 16/08 (2006.01); G11C 16/32 (2006.01); G11C 5/14 (2006.01); G11C 8/12 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 16/08 (2013.01); G11C 16/32 (2013.01); G11C 5/145 (2013.01); G11C 8/12 (2013.01); G11C 16/30 (2013.01);
Abstract

A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.


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