The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2018
Filed:
Apr. 17, 2015
Samsung Electronics Co., Ltd., Suwon-si, KR;
Chul-Hong Park, Seongnam-si, KR;
Sang-Hoon Baek, Seoul, KR;
Su-Hyeon Kim, Bucheon, KR;
Kyoung-Yun Baek, Suwon, KR;
Sung-Wook Ahn, Seoul, KR;
Sang-Kyu Oh, Gwacheon-si, KR;
Seung-Jae Jung, Hwaseong-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.