The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2018
Filed:
Oct. 05, 2015
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Raguram Damodaran, Raleigh, NC (US);
Joseph Raymond Michael Zbiciak, Farmers Branch, TX (US);
Naveen Bhoria, Plano, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0888 (2016.01); G06F 12/0897 (2016.01); G06F 12/12 (2016.01); G06F 12/0862 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0888 (2013.01); G06F 12/0862 (2013.01); G06F 12/0897 (2013.01); G06F 12/12 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/6022 (2013.01);
Abstract
The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.