The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

Dec. 17, 2015
Applicant:

Coherent Logix, Incorporated, Austin, TX (US);

Inventors:

John Mark Beardslee, Menlo Park, CA (US);

Michael B. Doerr, Dripping Springs, TX (US);

Tommy K. Eng, Pleasanton, CA (US);

Assignee:

Coherent Logix, Incorporated, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 9/44 (2006.01); G06F 9/54 (2006.01); G06F 9/52 (2006.01);
U.S. Cl.
CPC ...
G06F 8/41 (2013.01); G06F 8/30 (2013.01); G06F 8/451 (2013.01); G06F 9/52 (2013.01); G06F 9/54 (2013.01); G06F 9/546 (2013.01);
Abstract

A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a programming language. The source code specifies a plurality of tasks and communication of data among the plurality of tasks. However, the source code may not (and preferably is not required to) 1) explicitly specify which physical processor will execute each task and 2) explicitly specify which communication mechanism to use among the plurality of tasks. The method then creates machine language instructions based on the source code, wherein the machine language instructions are designed to execute on the plurality of processors. Creation of the machine language instructions comprises assigning tasks for execution on respective processors and selecting communication mechanisms between the processors based on location of the respective processors and required data communication to satisfy system requirements.


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