The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Dec. 31, 2014
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Dominique Ho, Singapore, SG;

Kwee Chong Chang, Singapore, SG;

Kah Weng Lee, Singapore, SG;

Brian J. Misek, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/06 (2006.01); H02M 1/32 (2007.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/60 (2006.01); H01L 23/58 (2006.01); H01L 23/48 (2006.01); H01L 23/495 (2006.01); H01L 23/522 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H02M 3/06 (2013.01); H01L 23/3107 (2013.01); H01L 23/48 (2013.01); H01L 23/49537 (2013.01); H01L 23/49575 (2013.01); H01L 23/5223 (2013.01); H01L 23/58 (2013.01); H01L 23/60 (2013.01); H01L 24/05 (2013.01); H01L 24/49 (2013.01); H01L 25/0657 (2013.01); H02M 1/32 (2013.01); H01L 23/49551 (2013.01); H01L 24/48 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48257 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06575 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/07025 (2013.01); H01L 2924/172 (2013.01); H01L 2924/1711 (2013.01); H01L 2924/3025 (2013.01); H01L 2924/386 (2013.01);
Abstract

A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.


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