The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Nov. 16, 2016
Applicant:

Intersil Americas Llc, Milpitas, CA (US);

Inventors:

Dev Alok Girdhar, Indialantic, FL (US);

Jeffrey Michael Johnston, Indian Harbour Beach, FL (US);

Assignee:

INTERSIL AMERICAS LLC, Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 27/088 (2006.01); H01L 23/535 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1087 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H01L 27/088 (2013.01); H01L 29/0692 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/66568 (2013.01); H01L 29/78 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Methods for forming body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a method comprises: forming a plurality of gates disposed on a semiconductor layer, each gate extending parallel to a y-axis in a coordinate space; a source region disposed between two of the plurality of gates; a plurality of body contacts disposed in each source region; and wherein a portion of each body contact, adjacent to the gate, has a width extending parallel to the y-axis that is less than the width of the body contact parallel to the y-axis at a distance on an x-axis from the gate.


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