The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Aug. 30, 2016
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Paolo Colpani, Agrate Brianza, IT;

Antonella Milani, Cusano Milanino, IT;

Lucrezia Guarino, Milan, IT;

Andrea Paleari, Brugherio, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/03 (2013.01); H01L 2224/02205 (2013.01); H01L 2224/02215 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05018 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05562 (2013.01); H01L 2224/05655 (2013.01); H01L 2924/04642 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/351 (2013.01);
Abstract

In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a 'dummy' via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10m.) and approximately 10 micron (10m.) from each one of said converging sides landing on an underlying metal layer.


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