The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Feb. 02, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Chulmin Jung, San Diego, CA (US);

Fahad Ahmed, San Diego, CA (US);

Sei Seung Yoon, San Diego, CA (US);

Keejong Kim, Phoenix, AZ (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/02 (2006.01); G11C 7/00 (2006.01); G11C 7/08 (2006.01); G11C 7/14 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 29/02 (2006.01); G11C 29/14 (2006.01); G11C 29/50 (2006.01); G11C 5/06 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/02 (2013.01); G11C 7/00 (2013.01); G11C 7/08 (2013.01); G11C 7/14 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 29/02 (2013.01); G11C 29/14 (2013.01); G11C 29/50012 (2013.01); G11C 5/06 (2013.01); G11C 7/062 (2013.01); G11C 7/10 (2013.01); G11C 29/026 (2013.01);
Abstract

A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.


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