The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Jun. 15, 2015
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Aniruddha Satoskar, Austin, TX (US);

Daniel J. Allen, Austin, TX (US);

Edmund Mark Schneider, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04R 3/02 (2006.01); G10K 11/175 (2006.01); H03M 1/18 (2006.01); H04R 3/00 (2006.01); H03M 1/00 (2006.01); H03M 1/06 (2006.01); H03M 3/00 (2006.01); H04H 20/10 (2008.01);
U.S. Cl.
CPC ...
G10K 11/175 (2013.01); H03M 1/002 (2013.01); H03M 1/0631 (2013.01); H03M 1/188 (2013.01); H03M 3/466 (2013.01); H04H 20/10 (2013.01); H04R 3/00 (2013.01);
Abstract

In accordance with embodiments of the present disclosure, a processing system may include multiple selectable processing paths for processing an analog signal in order to reduce noise, increase dynamic range, and mask audio artifacts associated with a change in noise floor. Techniques are employed to transition between processing paths and calibrate operational parameters of the two paths in order to reduce or eliminate artifacts caused by switching between processing paths.


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Satoskar, Aniruddha. (2018). Systems and methods for reducing artifacts and improving performance of a multi-path analog-to-digital converter (U.S. Patent No. 9959856). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9959856

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