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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9959500 B1

PDFFull Text
Date of Patent:
May. 01, 2018

Filed:

Jul. 05, 2017

Embedded spin transfer torque memory for cellular neural network based processing unit

Applicant:

Gyrfalcon Technology Inc., Milpitas, CA (US);

Inventors:

Chyu-Jiuh Torng, Dublin, CA (US);

Qi Dong, San Jose, CA (US);

Lin Yang, Milpitas, CA (US);

Assignee:

GYRFALCON TECHNOLOGY INC., Milpitas, CA (US);

Attorney:

Brinks, Gilson & Lione

Primary Examiner:

Victor A Mandala

Int. Cl.
CPC ...
H01L 27/22 (2006.01); G06N 3/06 (2006.01); H01L 27/06 (2006.01); H01L 23/535 (2006.01); H01L 43/08 (2006.01); H01L 23/528 (2006.01); H01L 43/02 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 43/12 (2006.01); H01L 21/768 (2006.01); H01L 21/321 (2006.01); G06N 3/08 (2006.01);
U.S. Cl.
CPC ...
G06N 3/061 (2013.01); G06N 3/08 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/535 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H01L 23/53295 (2013.01); H01L 27/0688 (2013.01); H01L 27/222 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01);
Abstract

An integrated circuit processor having a processing unit that includes a logical circuit with multiple transistors and a top metal landing pad, and an embedded STT memory. The STT memory includes a dielectric layer formed on the top metal landing pad, an adhesion and topography planarization (ATP) layer formed on the dielectric layer, and an MTJ film layer disposed on the ATP layer. The memory may also include bit lines formed on the MTJ film layer. The ATP layer may have multiple layers such as a top layer and a bottom layer. The top layer may act as an etch stop for etching the MTJ film layer on the top. The ATP layer may have a total thickness of 500 A to 4000 A. The bit lines can be configured to send data to the logic circuit of the processing unit to perform one or more convolution neural network computations.

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