The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2018
Filed:
Nov. 04, 2016
Motivo, Inc., Sunnyvale, CA (US);
Vito Dai, Santa Clara, CA (US);
Edward Kah Ching Teoh, San Jose, CA (US);
Ji Xu, San Jose, CA (US);
Bharath Rangarajan, Sunnyvale, CA (US);
Motivo, Inc., Sunnyvale, CA (US);
Abstract
Methods for integrated circuit design are provided. In one embodiment, a method for determining a physical layout pattern includes accessing a layout pattern configuration graph. The graph includes layout pattern configurations meeting a circuit requirements. At least two of the layout pattern configurations are annotated with characteristics by analyzing sample layout patterns. An integrated circuit electrical design is partitioned into circuit design configurations. One of the circuit design configurations meets one of the circuit requirements. One of the layout pattern configurations is selected from the layout pattern configuration graph to meet the selected circuit requirements. In another embodiment, a method for determining a netlist for an integrated circuit electrical design is provided. In a further embodiment, a method for determining a tool configuration for a manufacturing process is provided.