The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2018
Filed:
May. 13, 2015
Applicant:
Wisconsin Alumni Research Foundation, Madison, WI (US);
Inventors:
Hao Wang, Madison, WI (US);
Nam Sung Kim, Middleton, WI (US);
Assignee:
Wisconsin Alumni Research Foundation, Madison, WI (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/0802 (2016.01); G11C 13/00 (2006.01); G06F 3/06 (2006.01); G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 3/0604 (2013.01); G06F 3/0611 (2013.01); G06F 3/0638 (2013.01); G06F 3/0647 (2013.01); G06F 3/0683 (2013.01); G11C 11/005 (2013.01); G11C 13/0004 (2013.01); G11C 13/0021 (2013.01); G11C 13/0023 (2013.01); G06F 2212/60 (2013.01); G11C 2207/005 (2013.01);
Abstract
An architecture for improved memory access in asymmetric memories provides a set of shared row buffers that may be freely allocated between slow and fast memory banks of the asymmetric memory. This permits allocation of row buffers dynamically between the slow and fast memory banks to improve execution speeds and also permits a lightweight memory swap procedure for moving data between the slow and fast memory banks with low processor and memory channel overheads.