The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Apr. 24, 2013
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Michael D. Estlick, Fort Collins, CO (US);

Jay E. Fleischman, Fort Collins, CO (US);

Kevin A. Hurd, Fort Collins, CO (US);

Mark M. Gibson, Timnath, CO (US);

Kelvin D. Goveas, Austin, TX (US);

Brian M. Lay, Boulder, CO (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 9/46 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3828 (2013.01); G06F 9/3836 (2013.01); G06F 9/3838 (2013.01); G06F 9/3873 (2013.01); G06F 9/3889 (2013.01);
Abstract

A method includes allocating a first single-cycle instruction to a first pipeline that picks single-cycle instructions for execution in program order. The method further includes marking at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to all older single-cycle instructions allocated to the first pipeline being ready and eligible to be picked for execution. An apparatus includes a decoder to decode a first single-cycle instruction and to allocate the first single-cycle instruction to a first pipeline. The apparatus further includes a scheduler to pick single-cycle instructions for execution by the first pipeline in program order and to mark at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to determining that all older single-cycle instructions allocated to the first pipeline are ready and eligible.


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