The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

May. 29, 2014
Applicant:

Mill Computing, Inc., Palo Alto, CA (US);

Inventors:

Roger Rawson Godard, East Palo Alto, CA (US);

Arthur David Kahlich, Sunnyvale, CA (US);

David Arthur Yost, Los Altos, CA (US);

Assignee:

MILL COMPUTING, INC., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01); G06F 12/08 (2016.01); G06F 9/30 (2018.01); G06F 12/0875 (2016.01); G06F 12/0886 (2016.01);
U.S. Cl.
CPC ...
G06F 9/30149 (2013.01); G06F 9/382 (2013.01); G06F 9/3822 (2013.01); G06F 12/0875 (2013.01); G06F 12/0886 (2013.01); G06F 2212/452 (2013.01);
Abstract

A computer processor including an instruction buffer configured to store at least one variable-length instruction having a bit bundle bounded by a head end and a tail end with a plurality of slots each defining a corresponding operation, wherein the plurality of slots and corresponding operations are logically partitioned into a plurality of distinct blocks with a first group of blocks extending from the head end of the bit bundle toward the tail end of the bit bundle and a second group of blocks extending from the tail end of the bit bundle toward the head end of the bit bundle, wherein the second group of blocks includes a tail end block disposed adjacent the tail end of the bit bundle. A decode stage is operably coupled to the instruction buffer and configured to process a given variable-length instruction stored by the instruction buffer by decoding at least one operation of a particular block belonging to the first group of blocks in parallel with decoding at least one operation of the tail end block. Additional aspects are described and claimed.


Find Patent Forward Citations

Loading…