The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2018
Filed:
Jun. 24, 2016
Applicant:
Invecas, Inc., Santa Clara, CA (US);
Inventors:
Narasimhan Vasudevan, San Diego, CA (US);
Venkata N. S. N. Rao, Fremont, CA (US);
Prasad Chalasani, San Jose, CA (US);
Assignee:
Invecas, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/081 (2006.01); H03L 7/083 (2006.01); H03L 7/091 (2006.01); G11C 11/4063 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0818 (2013.01); G11C 7/222 (2013.01); G11C 11/4063 (2013.01); H03L 7/083 (2013.01); H03L 7/091 (2013.01);
Abstract
A master-slave delay locked loop system comprises a master delay locked loop ('MDLL') and at least one slave delay locked loop ('SDLL'). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.