The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Oct. 20, 2014
Applicant:

Agency for Science, Technology and Research, Singapore, SG;

Inventors:

Lakshmi Kanta Bera, Singapore, SG;

Surani Bin Dolmanan, Singapore, SG;

Manippady Krishna Kumar, Singapore, SG;

Rasanayagam Sivasayan Kajen, Singapore, SG;

Sudhiranjan Tripathy, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/20 (2006.01); H01L 29/45 (2006.01); H01L 21/283 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/324 (2006.01); H01L 21/02 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7783 (2013.01); H01L 21/0254 (2013.01); H01L 21/283 (2013.01); H01L 21/3085 (2013.01); H01L 21/31133 (2013.01); H01L 21/324 (2013.01); H01L 29/2003 (2013.01); H01L 29/452 (2013.01); H01L 29/66462 (2013.01); H01L 29/66522 (2013.01); H01L 29/66553 (2013.01); H01L 29/7786 (2013.01); H01L 29/78 (2013.01); H01L 21/02458 (2013.01); H01L 21/02502 (2013.01); H01L 29/41766 (2013.01);
Abstract

There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a nucleation layer on a substrate; depositing a binary layer over the nucleation layer; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge or their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.


Find Patent Forward Citations

Loading…