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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9954063 B1

PDFFull Text
Date of Patent:
Apr. 24, 2018

Filed:

Apr. 20, 2016

Stacked planar double-gate lamellar field-effect transistor

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Josephine B. Chang, Bedford Hills, NY (US);

Michael A. Guillorn, Cold Springs, NY (US);

Gen P. Lauer, Yorktown Heights, NY (US);

Isaac Lauer, Yorktown Heights, NY (US);

Jeffrey W. Sleight, Ridgefield, CT (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorney:

Nathan M. Rau

Primary Examiner:

Shaun Campbell

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 21/3065 (2006.01); H01L 29/04 (2006.01); H01L 29/40 (2006.01); H01L 29/786 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1037 (2013.01); H01L 21/0217 (2013.01); H01L 21/02532 (2013.01); H01L 21/3065 (2013.01); H01L 21/32115 (2013.01); H01L 21/32134 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/0692 (2013.01); H01L 29/401 (2013.01); H01L 29/42356 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01); H01L 21/30604 (2013.01); H01L 2029/7858 (2013.01);
Abstract

A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

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