The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Apr. 01, 2016
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Tomonori Nishino, Tokyo, JP;

Syou Yanagisawa, Tokyo, JP;

Kentaro Agata, Tokyo, JP;

Nobuyuki Ishige, Tokyo, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01); G02F 1/1362 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1244 (2013.01); G02F 1/13452 (2013.01); G02F 1/13458 (2013.01); G02F 1/136204 (2013.01); G02F 1/136227 (2013.01);
Abstract

This invention aims at reducing the probability of short-circuiting between terminals in a display device in which an IC driver is connected by COG. Terminals for connection with the IC driver are formed in a terminal region of a TFT substrate (). The terminals are each comprised of a terminal metal (), a first through-bole formed in a first insulation film (), a second through-hole formed in a second insulation film (), a first ITO () formed in the first through-hole and being in contact with the terminal metal (), and a second ITO () formed over the first ITO (). The second ITO () is formed within an area where the second ITO is in contact with the first ITO but is not formed outside the second through-hole. This ensures that the distance between the ITOs of the adjacent terminals can be enlarged, whereby the probability of short-circuiting between the terminals can be lowered.


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