Independent vertical-gate 3-d nand memory circuit

Abstract

A memory array provided on a semiconductor substrate includes: (a) channel structures arranged in multiple layers above the semiconductor substrate, each channel structure extending along a first direction substantially parallel a surface of the semiconductor substrate; (b) gate structures each extending along a second direction substantially transverse to the first direction and each being adjacent one of the channel structures, separated therefrom by a layer of memory material; and (c) conductors provided to connect the gate structures with circuitry fabricated in the semiconductor substrate, wherein at each location where one of the gate structure adjacent one of the channel structures, a portion of the gate structure, a portion of the channel structure and the layer of memory material constitute a memory cell of the memory array. Two or more memory cells sharing a channel structure are connected in series to form a NAND string.