The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Apr. 10, 2014
Applicant:

Joled Inc., Tokyo, JP;

Inventors:

Hirofumi Nakagawa, Tokyo, JP;

Hiroshi Takahara, Osaka, JP;

Assignee:

JOLED INC., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/30 (2006.01); G09G 3/3258 (2016.01); G09G 3/3266 (2016.01); H01L 27/32 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3258 (2013.01); G09G 3/3266 (2013.01); G09G 2310/0283 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01); G11C 19/28 (2013.01); H01L 27/3244 (2013.01);
Abstract

A gate drive integrated circuit includes: clock terminals; a bidirectional buffer that is located between the clock terminals and controls the input-output direction of a clock signal; a connection mode control terminal that receives a connection mode control signal; and a pair of signal direction control terminals that receive a signal direction control signal, wherein the bidirectional buffer fixes the input-output direction of the clock signal to one direction in the case where the logic state of the connection mode control signal is a first logic state, and switches the input-output direction of the clock signal depending on the logic state of the signal direction control signal in the case where the logic state of the connection mode control signal is a second logic state different from the first logic state.


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