The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Jan. 07, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Daniel J. Friedman, Sleepy Hollow, NY (US);

Seongwon Kim, Old Tappan, NJ (US);

Chung H. Lam, Peekskill, NY (US);

Dharmendra S. Modha, San Jose, CA (US);

Bipin Rajendran, White Plains, NY (US);

Jose A. Tierno, Stamford, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/06 (2006.01); G06N 3/04 (2006.01); G06N 3/063 (2006.01); G11C 11/54 (2006.01); G11C 13/00 (2006.01); G06N 3/08 (2006.01);
U.S. Cl.
CPC ...
G06N 3/06 (2013.01); G06N 3/049 (2013.01); G06N 3/063 (2013.01); G06N 3/0635 (2013.01); G06N 3/08 (2013.01); G11C 11/54 (2013.01); G11C 13/0004 (2013.01);
Abstract

Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.


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