The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Feb. 20, 2015
Applicant:

Khalifa University of Science and Technology, Abu Dhabi, AE;

Inventors:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/406 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 11/4072 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0652 (2013.01); G06F 3/0608 (2013.01); G06F 3/0673 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 8/10 (2013.01); G11C 11/406 (2013.01); G11C 11/4072 (2013.01); G11C 11/4087 (2013.01); G11C 11/4093 (2013.01);
Abstract

A method of erasing volatile memory requiring refreshment using refresh circuitry to maintain data storage, the method comprising controlling the refresh circuitry for preventing refreshment of the memory upon occurrence of a predefined event which would require erasure of data stored in the memory by a previous user, process, application or service. A computer readable medium encoded with processor executable instructions for execution by a processing unit for controlling a refresh circuitry connected to a volatile memory for preventing refreshment of the memory at the predefined event. A refresh circuitry adapted to be connected to a volatile memory requiring refreshment using the refresh circuitry to maintain data storage, the refresh circuitry being adapted to prevent the refreshment of the memory at the occurrence of the predefined event. A volatile memory comprising a refresh circuitry adapted to prevent the refreshment of the memory at the occurrence of the predefined event.


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