The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Jul. 31, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Malcolm S. Allen-Ware, Austin, TX (US);

Michael S. Floyd, Cedar Park, TX (US);

Joshua D. Friedrich, Round Rock, TX (US);

Charles R. Lefurgy, Austin, TX (US);

Kirk D. Peterson, Jericho, VT (US);

Karthick Rajamani, Austin, TX (US);

Srinivasan Ramani, Cary, NC (US);

Todd J. Rosedahl, Zumbrota, MN (US);

Gregory S. Still, Raleigh, NC (US);

Brian W. Thompto, Austin, TX (US);

Victor Zyuban, Yorktown Heights, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/324 (2013.01); G06F 1/3203 (2013.01); G06F 1/3206 (2013.01); G06F 1/3243 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1239 (2013.01);
Abstract

A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.


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