The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Jun. 14, 2016
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventor:

Yoshikazu Katoh, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); H04L 9/32 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01); G11C 7/24 (2006.01);
U.S. Cl.
CPC ...
H04L 9/3278 (2013.01); G11C 7/24 (2013.01); G11C 13/0002 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0059 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); G11C 2213/32 (2013.01);
Abstract

A non-volatile memory device according to an aspect of the present disclosure includes a memory array that includes non-volatile memory cells; a read circuit that, in operation, selects, from the memory array, non-volatile memory cells corresponding to one of resistance value ranges, and obtains pieces of resistance value information about resistance values of the selected non-volatile memory cells; a computation circuit that, in operation, calculates a binarization reference value by using the pieces of resistance value information; and an identification information generation circuit that, in operation, generates individual identification information. The read circuit, in operation, obtains first digital data in accordance with relationships between each of the pieces of resistance value information and the binarization reference value. The identification information generation circuit, in operation, obtains second digital data uncorrelated with the resistance values, and generates the individual identification information by using the first digital data and the second digital data.


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