The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2018
Filed:
Jun. 08, 2016
Applicant:
Intel Deutschland Gmbh, Neubiberg, DE;
Inventors:
Guenter Maerzinger, Linz, AT;
Bernd Adler, Neubiberg, DE;
Assignee:
Intel Deutschland GmbH, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/40 (2015.01); H04B 1/403 (2015.01); H04L 7/033 (2006.01); H03L 7/23 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0331 (2013.01); H03L 7/23 (2013.01); H04B 1/40 (2013.01); H04L 7/0012 (2013.01); H04L 7/033 (2013.01);
Abstract
A frequency generator for providing one or more clock signals with reduced phase jitter can include a phase-locked loop (PLL) configured to couple with a crystal and to provide a first clock signal, a multiplier circuit configured to receive the first clock signal and to provide a second clock signal, the second clock signal having a higher frequency than the first clock signal, wherein the multiplier circuit includes a second PLL, and wherein the second clock signal is an output frequency signal of the frequency generator.