The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Mar. 06, 2017
Applicant:

Apresia Systems, Ltd., Minato-ku, Tokyo, JP;

Inventor:

Daisuke Fujiu, Tsuchiura, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 7/04 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0008 (2013.01); H04L 7/04 (2013.01);
Abstract

Provided is a communication apparatus usable for any case where a time synchronization function is necessary or unnecessary by attaching or detaching a synchronization model for realizing the time synchronization function. A clock generation unit, a logic circuit unit including a synchronization module monitoring unit, a clock selection unit, and a main circuit unit configured by a switch LSI are integrally formed on the same substrate, and the synchronization module is detachably mounted on the substrate via connectors. The connectors each have a mounting determination pin that indicates a different signal level depending on whether the synchronization module is mounted. The synchronization module monitoring unit monitors connection signals indicating signal levels of the mounting determination pin, and causes the clock selection unit to select a synchronization clock when the synchronization module is mounted, and an internal clock when the synchronization module is not mounted.


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