The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2018
Filed:
May. 03, 2016
Applicant:
Soctronics, Inc., Santa Clara, CA (US);
Inventors:
Prasad Chalasani, San Jose, CA (US);
Venkata N. S. N. Rao, Fremont, CA (US);
Assignee:
SoCtronics, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/04 (2006.01); G06F 1/12 (2006.01); G06F 1/14 (2006.01); H04L 7/00 (2006.01); H03L 7/00 (2006.01); H03K 19/0175 (2006.01); G06F 13/38 (2006.01); G06F 1/08 (2006.01); H03L 7/08 (2006.01); H03L 7/093 (2006.01); G06F 1/28 (2006.01); G06F 1/10 (2006.01); H04L 25/02 (2006.01); G06F 1/06 (2006.01);
U.S. Cl.
CPC ...
H03L 7/00 (2013.01); G06F 1/04 (2013.01); G06F 1/06 (2013.01); G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01); G06F 1/14 (2013.01); G06F 1/28 (2013.01); G06F 13/385 (2013.01); H03K 19/0175 (2013.01); H03K 19/017509 (2013.01); H03L 7/0802 (2013.01); H03L 7/093 (2013.01); H04L 7/0012 (2013.01); H04L 25/028 (2013.01); H04L 25/0276 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract
A method for clocking a physical layer ('PHY') and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.