The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2018
Filed:
Jun. 26, 2017
Applicant:
Altera Corporation, San Jose, CA (US);
Inventors:
Navid Azizi, Markham, CA;
Gordon Raymond Chiu, North York, CA;
Michael Howard Kipper, Thornhill, CA;
Assignee:
ALTERA CORPORATION, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/20 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
H03K 19/20 (2013.01); G06F 17/50 (2013.01); G06F 17/5045 (2013.01);
Abstract
Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.