The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Feb. 28, 2017
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Masato Oda, Yokohama, JP;

Shinichi Yasuda, Setagaya, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); H01L 25/00 (2006.01); H03K 19/173 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1737 (2013.01); H01L 23/5252 (2013.01); H03K 19/1735 (2013.01); H03K 19/1776 (2013.01); H03K 19/17728 (2013.01);
Abstract

An integrated circuit of an embodiment includes: a first to third wiring lines; a first and second input terminals connected to the second and third wiring lines respectively; a first and second control terminals; a first switch element disposed between the first and second wiring lines, the first switch element including a first and second terminals connected to the first and second wiring lines respectively; a second switch element disposed between the first and third wiring lines, the second switch element including a third and fourth terminals connected to the first and fourth terminals connected to the first and third wiring lines respectively; a first transistor including a source and a drain, one of the source and the drain being connected to the first wiring line; a select circuit including a fifth to eighth terminals; and a logic circuit including a ninth to eleventh terminals.


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