The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

May. 31, 2016
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Douglas Stuart Smith, Milpitas, CA (US);

Vladislav Vashchenko, Palo Alto, CA (US);

Augusto Tazzoli, San Jose, CA (US);

Sudhir Mulpuru, Milpitas, CA (US);

Lawrence Richard Skrenes, Hartland, WI (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
A61B 5/00 (2006.01); H02H 9/04 (2006.01); A61B 5/0408 (2006.01); A61B 5/0428 (2006.01); A61N 1/39 (2006.01);
U.S. Cl.
CPC ...
H02H 9/045 (2013.01); A61B 5/0408 (2013.01); A61B 5/0428 (2013.01); A61N 1/3931 (2013.01);
Abstract

Silicon-controlled rectifier (SCR) based circuit for ECG protection under defibrillator pulse is disclosed. The SCR-based clamp is a symmetric structure for dual-direction voltage tolerance protection based on two anti-series P-well/N-well lateral blocking junctions isolated from P-substrate by the N-buried layer. The injector regions (n+/p+) are substantially lengthened in order to accommodate a larger number of contact rows than typically used for ESD pulses specification. A stack of metal layers may also be used to provide high current and heat-sink capability with each electrode metal layer fully filled with VIAs.


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