The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Jan. 17, 2008
Applicants:

Jian LI, Palo Alto, CA (US);

Kuo-in Chen, Los Altos, CA (US);

Kyle Terril, Santa Clara, CA (US);

Inventors:

Jian Li, Palo Alto, CA (US);

Kuo-In Chen, Los Altos, CA (US);

Kyle Terril, Santa Clara, CA (US);

Assignee:

Vishay-Siliconix, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66734 (2013.01); H01L 29/1095 (2013.01); H01L 29/41766 (2013.01); H01L 29/66719 (2013.01); H01L 29/66727 (2013.01); H01L 29/7813 (2013.01); H01L 29/456 (2013.01); H01L 29/4925 (2013.01); H01L 29/4933 (2013.01);
Abstract

A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.


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