The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Jun. 08, 2017
Applicant:

Infineon Technologies Dresden Gmbh, Dresden, DE;

Inventors:

Dmitri Alex Tschumakow, Dresden, DE;

Claus Dahl, Dresden, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/331 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/737 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66242 (2013.01); H01L 29/0804 (2013.01); H01L 29/0817 (2013.01); H01L 29/66234 (2013.01);
Abstract

A method for manufacturing a bipolar junction transistor is provided. A layer stack is provided that comprises a semiconductor substrate having a trench isolation; an isolation layer arranged on the semiconductor substrate, wherein the first isolation layer comprises a recess forming an emitter window; lateral spacers arranged on sidewalls of the emitter window; a base layer arranged in the emitter window on the semiconductor substrate; and an emitter layer arranged on the isolation layer, the lateral spacers and the base layer. A sacrificial layer is provided on the emitter layer thereby overfilling a recess formed by the emitter layer due to the emitter window. The sacrificial layer is selectively removed up to the emitter layer while maintaining a part of the sacrificial layer filling the recess of the emitter layer. The emitter layer is selectively removed up to the isolation layer while maintaining the filled recess of the emitter layer.


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