The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Feb. 13, 2015
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventor:

Hiroaki Sekikawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 21/82 (2006.01); H01L 27/14 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14636 (2013.01); H01L 21/82 (2013.01); H01L 27/14 (2013.01); H01L 27/14607 (2013.01); H01L 27/14612 (2013.01); H01L 27/14621 (2013.01); H01L 27/14623 (2013.01); H01L 27/14627 (2013.01); H01L 27/14643 (2013.01); H01L 27/14683 (2013.01); H01L 27/14687 (2013.01); H01L 23/522 (2013.01);
Abstract

A semiconductor device includes a plurality of wirings (WR) which are formed in the same layer above a semiconductor substrate, and a plurality of wirings (WR) which are formed in the same layer as that of the plurality of wirings (WR). The plurality of wirings (WR) are extended in an X axis direction and arranged at a pitch (PT) in a Y axis direction intersecting with the X axis direction when seen in a plan view, and the plurality of wirings (WR) are extended in the X axis direction and arranged at a pitch (PT) in the Y axis direction when seen in a plan view. The plurality of wirings (WR) are electrically connected to the plurality of wirings (WR), and the pitch (PT) is smaller than the pitch (PT).


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