The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Jul. 16, 2017
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, CN;

Inventors:

Shimin Ge, Shenzhen, CN;

Hejing Zhang, Shenzhen, CN;

Chihyuan Tseng, Shenzhen, CN;

Chihyu Su, Shenzhen, CN;

Wenhui Li, Shenzhen, CN;

Longqiang Shi, Shenzhen, CN;

Xiaowen Lv, Shenzhen, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/49 (2006.01); H01L 29/24 (2006.01); H01L 21/02 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1288 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 29/24 (2013.01); H01L 29/4908 (2013.01); H01L 29/7869 (2013.01); H01L 29/78648 (2013.01); H01L 27/3262 (2013.01);
Abstract

A method for manufacturing a dual gate oxide semiconductor TFT substrate utilizes a halftone mask to implement a photo process, which not only accomplishes patterning to an oxide semiconductor layer but also obtains an oxide conductor layer with ion doping. The method implements patterning to a bottom gate isolation layer and a top gate isolation layer at the same time with one photolithographic process. The method implements patterning to second and third metal layers at the same time to obtain a first source, a first drain, a second source, a second drain, a first top gate and a second top gate with one photolithographic process. The method implements patterning to a second flat layer, a passivation layer and a top gate isolation layer at the same time with one photolithographic process. The number of photolithographic processes involved is reduced to nine so as to simplify the manufacturing process.


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