The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9947467 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 17, 2018

Filed:

Apr. 24, 2017
Applicant:

Mjg Innovations, Llc, Fort Worth, TX (US);

Inventor:

Mark Eugene Goodson, Corinth, TX (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01G 2/14 (2006.01); H02H 9/04 (2006.01); H05K 1/18 (2006.01); H01G 2/10 (2006.01); H01G 2/06 (2006.01); H05K 3/32 (2006.01); H02H 9/00 (2006.01); H01L 29/872 (2006.01); H02H 3/16 (2006.01);
U.S. Cl.
CPC ...
H01G 2/14 (2013.01); H01G 2/06 (2013.01); H01G 2/10 (2013.01); H02H 9/005 (2013.01); H02H 9/04 (2013.01); H02H 9/041 (2013.01); H02H 9/044 (2013.01); H05K 1/181 (2013.01); H05K 3/32 (2013.01); H01L 29/872 (2013.01); H02H 3/165 (2013.01); H02H 9/043 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10174 (2013.01); H05K 2201/10196 (2013.01);
Abstract

A protected capacitor system/method implementing enhanced transient over-voltage suppression is disclosed. The system/method incorporates one or more surge suppression devices (SSDs) proximally located and in parallel with a capacitor structure to produce an overall protected capacitor structure having enhanced reliability and simultaneous ability to resist transient overvoltage conditions. The SSDs are formed from series combinations of transient voltage surge suppressors (TVSs) (metal oxide varistor (MOV), diode for alternating current (DIAC), and/or silicon diode for alternating current (SIDAC)) and corresponding shunt diode rectifiers (SDRs) and placed in parallel across a capacitor structure to locally suppress voltage transients across the capacitor structure in excess of the voltage rating of the capacitor structure. The parallel shunting TVS/SDR pairs may be integrated into a printed circuit board (PCB) assembly that is externally attached to the capacitor structure or encapsulated in an enclosure incorporating the capacitor structure.


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